Citation: Proceedings of the 2017 Federated Conference on Computer Science and Information Systems, M. Ganzha, L. Maciaszek, M. Paprzycki (eds). ACSIS, Vol. 11, pages 523–526 (2017)
Abstract. A significant challenge in numerical programming modern architectures is to effectively exploit the parallelism available in the architecture and manage the fast memories to maximize performance. Loop nest tiling allows for both coarsening parallel code and improving code locality. In this paper, we explore a new way to generate tiled code and derive the free schedule of tiles. It is based on the transitive closure of loop nest dependence graphs. Tiles are executed as soon as their operands are available. To describe and implement the approach, loop dependences are presented in the form of tuple relations. Discussed techniques are implemented in the open source TRACO compiler. Experimental results carried out on multi-core architectures demonstrate the considerable speed-ups of tiled numerical codes generated by the presented approach.
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