Logo PTI
Polish Information Processing Society
Logo FedCSIS

Annals of Computer Science and Information Systems, Volume 21

Proceedings of the 2020 Federated Conference on Computer Science and Information Systems

Testbed for thermal and performance analysis in MPSoC systems

, , ,

DOI: http://dx.doi.org/10.15439/2020F174

Citation: Proceedings of the 2020 Federated Conference on Computer Science and Information Systems, M. Ganzha, L. Maciaszek, M. Paprzycki (eds). ACSIS, Vol. 21, pages 683692 ()

Full text

Abstract. Many modern computing platforms in the safety-critical domains are based on heterogeneous Multiprocessor System-on-Chip (MPSoC). Such computing platforms are expected to guarantee high-performance within a strict thermal envelope. This paper introduces a testbed for thermal and performance analysis. The testbed allows the users to develop advanced scheduling and resource allocation techniques aiming at finding an optimal trade-off between the peak temperature and the achieved performance. This paper presents a new, open-source Thermobench tool for data collection and analysis of user-defined workloads. Furthermore, a methodology for shortening the time needed for the data collection is proposed. Experiments show that a significant amount of time can be saved. Specifically, time reduction from 60 minutes to 15 minutes is achieved with the i.MX8 MPSoC from NXP while running a set of user-defined benchmarks that stress CPU, GPU, and different levels of the memory hierarchy.

References

  1. NXP. (2020). “i.MX 8QuadMax/QuadPlus Multisensory Enablement Kit,” [Online]. Available: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-8quadmax-multisensory-enablement-kit-mek:MCIMX8QM-CPU (visited on 07/02/2020).
  2. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan, “HotSpot: A compact thermal modeling methodology for early-stage VLSI design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 5, pp. 501–513, 2006. DOI : 10.1109/TVLSI.2006.876103.
  3. A. Kanduri, M. Haghbayan, A. M. Rahmani, M. Shafique, A. Jantsch, and P. Liljeberg, “adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning,” IEEE Transactions on Computers, vol. 67, no. 8, pp. 1062–1077, Aug. 2018, ISSN: 0018-9340. DOI : 10.1109/TC.2018.2805683.
  4. Y. Chandarli, N. Fisher, and D. Masson, “Response Time Analysis for Thermal-Aware Real-Time Systems under Fixed-Priority Scheduling,” in 2015 IEEE 18th International Symposium on Real-Time Distributed Computing, Apr. 2015, pp. 84–93. DOI : 10.1109/ISORC.2015.34.
  5. N. Bombieri, F. Busato, and F. Fummi, “Power-aware Performance Tuning of GPU Applications Through Microbenchmarking,” in Proceedings of the 54th Annual Design Automation Conference 2017, (Austin, TX, USA), ser. DAC ’17, New York, NY, USA: ACM, 2017, 66:1–66:6, ISBN : 978-1-4503-4927-7. http://dx.doi.org/10.1145/3061639.3062304. [Online]. Available: http://doi.acm.org/10.1145/3061639.3062304 (visited on 07/30/2019).
  6. E. Calore, A. Gabbana, S. F. Schifano, and R. Tripiccione, “Evaluation of DVFS techniques on modern HPC processors and accelerators for energy-aware applications,” Concurrency and Computation: Practice and Experience, vol. 29, no. 12, e4143, Jun. 25, 2017, ISSN: 1532-0626. DOI : 10.1002/cpe.4143. [Online]. Available: https://onlinelibrary.wiley.com/doi/full/10.1002/cpe.4143 (visited on 07/30/2019).
  7. J. Lucas and B. Juurlink, “MEMPower: Data-Aware GPU Memory Power Model,” in Architecture of Computing Systems – ARCS 2019, M. Schoeberl, C. Hochberger, S. Uhrig, J. Brehm, and T. Pionteck, Eds., ser. Lecture Notes in Computer Science, Springer International Publishing, 2019, pp. 195–207, ISBN : 978-3-030-18656-2.
  8. B. Johnston, B. Lee, L. Angove, and A. Rendell, “Embedded Accelerators for Scientific High-Performance Computing: An Energy Study of OpenCL Gaussian Elimination Workloads,” in 2017 46th International Conference on Parallel Processing Workshops (ICPPW), Aug. 2017, pp. 59–68. http://dx.doi.org/10.1109/ICPPW.2017.22.
  9. F. Muslim, A. Demian, L. Ma, L. Lavagno, and A. Qamar, “Energy-efficient FPGA implementation of the k-nearest neighbors algorithm using OpenCL,” in Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, M. Ganzha, L. Maciaszek, and M. Paprzycki, Eds., vol. 9, 2016, pp. 141–145. DOI : 10.15439/2016F327.
  10. C. Schlaak, M. Fakih, and R. Stemmer, “Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs,” presented at the International Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES), Jan. 13, 2017. https://arxiv.org/abs/ 1701 . 03709 [cs]. [Online]. Available: http://arxiv.org/abs/1701.03709 (visited on 08/02/2019).
  11. K. Dev, I. Paul, W. Huang, Y. Eckert, W. Burleson, and S. Reda, “Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques,” Aug. 29, 2018. https://arxiv.org/abs/ 1808 . 09651 [cs]. [Online]. Available: http://arxiv.org/abs/1808.09651 (visited on 09/17/2019).
  12. Y. Lee, K. G. Shin, and H. S. Chwa, “Thermal-Aware Scheduling for Integrated CPUs–GPU Platforms,” in EMSOFT’19, 2019. [Online]. Available: https://rtcl.eecs.umich.edu/rtclweb/assets/publications/2019/yml-emsoft.pdf.
  13. J. Perez Rodriguez and P. Meumeu Yomsi, “Thermalaware schedulability analysis for fixed-priority non-preemptive real-time systems,” in 2019 IEEE Real-Time Systems Symposium (RTSS), ISSN: 2576-3172, Dec. 2019, pp. 154–166. DOI : 10.1109/RTSS46320.2019.00024.
  14. S. Hosseinimotlagh and H. Kim, “Thermal-Aware Servers for Real-Time Tasks on Multi-Core GPU-Integrated Embedded Systems,” in 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Apr. 2019, pp. 254–266. DOI : 10.1109/RTAS.2019.00029.
  15. S. Pagani, H. Khdr, J. Chen, M. Shafique, M. Li, and J. Henkel, “Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon,” IEEE Transactions on Computers, vol. 66, no. 1, pp. 147–162, Jan. 2017. http://dx.doi.org/10.1109/TC.2016.2564969.
  16. S. Che, J. W. Sheaffer, M. Boyer, L. G. Szafaryn, L. Wang, and K. Skadron, “A characterization of the rodinia benchmark suite with comparison to contemporary CMP workloads,” in IEEE International Symposium on Workload Characterization (IISWC’10), Dec. 2010, pp. 1–11. http://dx.doi.org/10.1109/IISWC.2010.5650274.
  17. Workswell. (2020). “Workswell infrared camera,” [On-line]. Available: https://workswell-thermal-camera.com/workswell-infrared-camera-wic/#specifications (visited on 07/02/2020).
  18. Intel. (2020). “Minnowboard turbot,” [Online]. Available: https://software.intel.com/content/www/us/en/develop/topics/iot/hardware/minnow-board-turbot.html (visited on 07/02/2020).
  19. TE Connectivity. (2020). “Htu21d digital high accuracy rh/t sensor,” [Online]. Available: https://www.te.com/global-en/product-CAT-HSC0004.html (visited on 07/02/2020).
  20. Toshiba. (2020). “TB6612FNG,” [Online]. Available: https://toshiba.semicon-storage.com/ap-en/semiconductor/product/motor-driver-ics/brushed-dc-motor-driver-ics/detail.TB6612FNG.html (visited on 07/02/2020).
  21. F. T. Brown, Engineering System Dynamics: A Unified Graph-Centered Approach, Second Edition, 2 edition. Boca Raton, FL: CRC Press, Aug. 15, 2006, 1059 pp., ISBN: 978-0-8493-9648-9.