Path Length-Driven Hypergraph Partitioning: An Integer Programming Approach

Circuit prototyping on multi-FPGA (Field Programmable Gate Arrays) platforms is a widely used technique in the VLSI (Very-Large-Scale Integration) context. Due to the ever-increasing size of circuits, it is necessary to use partitioning algorithms to place them on multi-FPGA platforms. Existing partitioning algorithms focus on minimizing the cut size but do not consider the critical path length, which can be degraded when mapping long paths to multiple FPGAs. However, recent studies try to consider the degradation of the critical path and the target topology but these works still use cutting minimization algorithms. In this work, we propose a mathematical model as an integer program (IP) based on the Red-Black Hypergraph model that considers the minimization of the critical path degradation and the target topology. We compare our partitioning results with KHMETIS, a min-cut algorithm, and show a better critical path for many circuit instances.


I. INTRODUCTION
O UR work concerns practical improvements of the elec- tronic circuit design chain.The typical hardware design flow includes different steps, such as floor planning, placement, and routing, that may concern very large logic circuits.
To deal with such large circuits, the methods involved may benefit from divide-and-conquer approaches that allow for working locally on separate parts of the circuit, greatly reducing the work on the global circuit.Such a divide-and-conquer approach also enables circuit prototyping on a multi-FPGA platform, where the circuit is too large (in terms of resource consumption) to be implemented on a single FPGA.In such cases, a strong constraint is to mitigate a possible increase in the signal propagation delay of the longest combinatorial path, known as the critical path.Indeed, in synchronous circuits, the critical path length determines the maximum frequency at which the circuit may operate; mapping long paths across several FPGAs is likely to degrade the critical path.
Circuit partitioning is both an essential step in the design flow of electronic circuits, and a challenging multi-constraint optimization problem.It must address both the multi-resource issue (i.e., capacity limits on each FPGA and their interconnection links) and the minimization of the critical path degradation.
Traditional partitioning tools use the now classic multi-level scheme (see Fig. 1) consisting of three phases: coarsening, initial partitioning, and refinement [1].The coarsening phase C o n t r a c t i o n p h a s e R e f i n e m e n t p h a s e Initial partitioning Fig. 1.Multi-level scheme uses a recursive clustering method to transform the circuit model, a hypergraph, into a smaller one.During the second phase, an initial partitioning is computed on the smallest coarsened hypergraph.Finally, for each coarsening level, the solution for the coarser level is extended to the finer level and then refined using a local refinement algorithm.The initial partitioning algorithm presented in this paper concerns the first step of the multilevel framework described above.
Our work focuses on balanced hypergraph partitioning, in which our objective functions are both path-cost minimization and the classical min-cut objective that is still relevant to us.The hypergraph model we consider in our research context consists of a union of directed acyclic hypergraphs (DAH) [2].The global hypergraph is assumed to be connected; otherwise, its disconnected components are processed independently.The source and sink vertices of each DAH (which represent registers and I/O ports) are labeled red, while other vertices are black.Red vertices can be shared by multiple DAHs, which makes the global hypergraph connected.A path-cost function models the impact of a cut on the red-to-red paths during partitioning.Each partition of a hypergraph will result in cuts along some paths, inducing additional traversal costs.Our aim is to find a partition of minimum path cost, such that the size of the cut is also minimized.Our research context only considers the paths between two red vertices and a non-uniform cut cost between parts.
The classical approach is to model this problem with a hypergraph, using cost functions that minimize cut size.However, it has been shown in [3] that the cut size does not address the path cost efficiently during the hypergraph partitioning procedure.This is why several authors proposed pre-and/or post-processing steps in order to reduce the degradation of cut paths [3], [4], [5].In this paper, we devise a dedicated integer programming model that minimizes path cost degradation during partitioning, based on the red-black hypergraph structure, which can be used as an initial partitioning method in a multilevel framework.
The remainder of the paper is organized as follows: Section 2 presents a reminder of our red-black hypergraph structure as well as previous works.Section 3 describes our coarsening scheme before the initial partitioning and the integer programming model.Our experiments are outlined in Section 4. We conclude and give perspectives in Section 5.

II. PRELIMINARIES
In this part, we define the notations and definitions used in this work.

A. Definitions and Notations
Let H def = (V, A, W v , W a ) be a directed hypergraph, defined by a set of vertices V and a set of hyperarcs A, with a vertex weight function W v : V → R + and a hyperarc weight function W a : A − → R + .Every hyperarc a ∈ A is a subset of vertex set V: a ⊆ V. Let s + (a) be the source vertex set of hyperarc a, and s − (a) its sink (destination) vertex set.We consider here, without loss of generality, that each hyperarc has a single source, so ∀a, |s + (a)| = 1.As hyperarcs connect vertices, let Γ(v) be the set of neighbor vertices of vertex v, and Γ − (v) ⊆ Γ(v) and Γ + (v) ⊆ Γ(v) the sets of its inbound and outbound neighbors, respectively.
In the model we propose, hypergraphs that model circuits are be represented as sets of interconnected DAHs, according to a red-black vertex coloring scheme.Red vertices correspond to I/O (Inputs/Outputs) ports and registers, and black vertices to combinatorial circuit components.Let V R ⊂ V and V B ⊂ V be the red and black vertex subsets of V, such that , and no cycle path connects a vertex to itself.
Using this definition, we can represent circuit hypergraphs as red-black hypergraphs, i.e., sets of DAHs that share some of their red vertices.Let H(V, A) def = {H i , i ∈ {1 . . .n}} be a red-black hypergraph, such that every H i is a DAH and an edge-induced sub-hypergraph of H. Consequently, then H i and H j share source and/or sink vertices, i.e., V i,j ⊂ V R .
In this model, the paths in H to consider when addressing the objective of minimizing path-cost degradation during partitioning are only the paths interconnecting red vertices, as these red-red paths represent register-to-register paths in combinatorial circuits.Since only red vertices are shared between DAHs in H, red-red paths only exist within a single DAH and can never span across several DAHs.
Let us define P as the set of red-red paths in H, such that P def = {p|p is a path in H ∈ H}.From these paths and a function d max (u, v), which computes the maximum distance between vertices u and v of some DAH H, we can define the longest path distance for H as: ) and, by extension, for H, as: A partition Π of H is a splitting of V into vertex subsets π i , called parts, such that: (i) all parts π i , given a capacity bound M , respect the capacity constraint: (ii) all parts are pairwise disjoint: (iii) the union of all parts is equal to V: Consequently, in our model, the distance between two vertices u and v may increase during partitioning due to the additional cost of routing paths between two (or more) parts.Let D kk ′ be the penalty associated with parts k and k ′ such that if u is in part k and v is in part k ′ , then: For a given partition Π of H, the path-cost is defined by the function: Let a red-black hypergraph H and a partition Π, the connectivity λ Π (a) of some hyperarc a ∈ A is the number of parts connected by a.If λ Π (a) > 1, then a is said to be cut; otherwise, it is entirely contained within a single part and is not cut.The cut of partition Π is the set ω(Π) of cut hyperarcs, i.e., ω(Π) The cut size is defined as . If all hyperarcs have the same weight (equal to 1), the cut size is equal to |ω(Π)|.Another cut metric used by some partitioning tools to measure the quality of partitioning is called connectivity-minus-one [6].The connectivityminus-one cost function f λ of some partitioned hypergraph H Π is defined as:

B. Previous work
Several approaches in the literature have been attempted to improve the performance of circuit partitioning.We present some recent work on circuit partitioning for rapid prototyping that considers performance constraints.Many of these works attempt to tweak existing min-cut partitioning tools, which are used as black boxes, to consider additional constraints.For example, [3] presents a multi-objective approach based on HMETIS.The authors compute the K most critical paths at each partitioning step, using a metric cost that considers the critical path length, the cut number along critical paths, and the weight of the hyperarcs associated with the critical paths.Reference [4] compares a classical method using HMETIS for partitioning followed by a placement algorithm with a derived approach consisting of placement and routing during the partitioning step.The results show better critical path values compared to the two-step approach.More recently, [5] performs some pre-and post-processing on the hypergraph to capture the critical path minimization objective within the cut-size metric, using HMETIS as the partitioning tool.Reference [7], presents an IP model to address the hypergraph partitioning problem.The model is not dedicated to mapping and critical path minimization but to minimize the cut cost.

III. CONTRIBUTIONS
We now present our core contribution.The first part consists of a coarsening algorithm to reduce the size of the hypergraph.In the second part, we present our IP model used as initial partitioning.

A. Coarsening method
The heavy-edge matching (HEM) approach for graph coarsening presented in [8] is widely used in hypergraph and graph partitioning tools [9], [10] and yields efficient results in many cases.Our coarsening algorithm is based on a heavyedge matching approach.It consists of reducing the instance's size while minimizing the merged vertices' weight differences as much as possible.The risk in merging vertices is to end up with disproportionate weights of vertices, which may prevent the initial partitioning from exploring different solutions.However, in the context of critical path minimization, it may be interesting to merge all vertices along the critical path into one large vertex.This method is not necessarily interesting when the circuit contains many critical or semicritical paths.It is, therefore, necessary to find a compromise between creating a large vertex by securing the cut along the critical path and balancing the fusion to allow a more practical exploration search during the initial partitioning phase.The vertex criticality model the value of the longest path traversing the vertex.Our algorithm groups vertices by criticality to favor the grouping of critical paths.Vertices with a smaller weight are selected to favor balanced coarsening.

B. Integer Program
The objective of the IP model is to minimize the degradation of the critical path, so we need to calculate the maximum degradation among all possible degradations.We also need to model the target topology to consider the different delays between each part.Cut minimization tools do not address these two aspects: path length and topology.Cut minimization tools only limit the connections between parts.As this objective  is still essential in practice, we add a second objective to our model: minimizing the connectivity minus one.As the paths between two red vertices do not contain cycle, it is possible to see the chain of black vertices in a path as a sequence of operations/tasks i associated with a job l.In our model, we consider scheduling constraints to minimize the impact of partitioning on the critical path.Given a path (job) p = v 0 , v 1 , v 2 , the critical time associated with the path equals v∈p d v .If vertices (tasks) belonging to p are placed in different parts, then a time penalty must be added to the total time of p.A summary of the integer model can be found in Table I, the parameters in Table II, and the variables in Table III.Below is the integer program with two objectives 2a for critical path minimization and 2b for connectivity cost minimization: subject to : Constraint 2c states that each vertex is mapped onto one part.Constraint 2d guarantees that y jk equals the connectivity cost 1 iff the vertex i is mapped onto part k, 0 otherwise y jk 1 iff the hyperedge j has a vertex placed on part k z l completion time of job l zmax maximum completion time of jobs associated with hyperedge j.The constraint 2e ensures the capacity constraint is respected.The constraints 2f and 2g determine the value of the delay of the job (path) and the maximum delay (critical path).The constraint 2h are the nonnegativity and integrity conditions on the variable.
There are symmetries in the solution space in hypergraph partitioning for cut size minimization.Indeed, if there are ω hyperedges between parts, ω remains unchanged regardless of the labels of the parts.On the other hand, in our problem, we are trying to minimize the path cost, which is degraded by routing paths between parts that are not always fully connected.There are models for partitioning graphs and hypergraphs with symmetry-breaking constraints [11].However, these constraints are too restrictive for the solution space associated with path cost.In our problem, the target topology defines a time penalty associated with path routing.As a result, we cannot consider all partitions with the same subset of vertices but different labels, identical, from a routing point of view.An example can be found in Figure 2. Note that some symmetries exist, for example: if we take the partition a, shown in Figure 2. It is possible to create a partition a ′ by swapping the vertices of π 0 and π 3 and of π 1 and π 2 .Future work will involve improving the model to remove these symmetries.

IV. EXPERIMENTAL RESULTS
To validate our models and algorithms, we have performed experiments on benchmarks [12] of logic circuits.These circuits consist of acyclic combinatorial blocks, bounded by their input and output registers.Every combinatorial block can therefore be modeled as a DAH.Their computation time is conditioned by their critical path, defined as the longest path between two registers (i.e., two red vertices).Our work aims at minimizing the degradation of the critical path during partitioning according to the target topology.For each instance, we use topology data to define a traversal cost d(v) for each vertex v, corresponding to the traversal time of a logic element.As the degradation between the parts can be non-homogeneous, we have defined several architecture topologies composed of four elements.The test architecture is a chain π 0 , π 1 , π 2 , π 3 .We did not consider the fully connected topology to highlight the advantage of our topology-aware algorithms over regular partitioners like KHMETIS.To solve the initial partitioning problem, we use Gurobi Optimiser version 9.1.2with a time limit set to 600s.During the refinement phase, we use the DKFM [2], a local search algorithm dedicated to minimizing path length.This algorithm is inspired by FM [13], a local a) b) Fig. 2. In this example, the path p = v 0 , v 1 , v 2 , v 3 , v 4 , v 5 is partitioned into 4 parts.In partition a, the path admits a routing penalty of 3D, where D is the traversal time between parts.In partition b, the routing penalty is 5D.
Since there is no route between π 0 and π 2 , we must necessarily pass through π 1 to get there, which gives a cost of 2D to get from π 0 to π 2 .The same goes for π 1 to π 3 .From the point of view of the size of the cut, partition a allows a cost of 3 cut edges, as does partition b.Partitions a and b are identical and symmetrical for cut minimization.
search algorithm for minimising the number of hyperedges between two parts.We use KHMETIS rather than HMETIS because HMETIS is based on recursive bipartitioning methods, which often do not respect the balance constraint.We use the maximum criticality as a weight for the hyper-edges as [2] to guide KHMETIS to minimise the number of cuts along the critical path as much as possible.

A. Results
Table IV shows that our approach gives better results.Indeed, the first coarsening step allows the grouping of the most critical vertices while maintaining a balance in the reduced hypergraph.Finally, since the initial partitioning considers the topology, it allows for finding an appropriate placement before the refinement phase.For instances B14 and B17, the time limit is not sufficient for Gurobi to find a good solution.A method needs to be found to better reduce the size of the instance while retaining sufficient criticality information for the integer program.  of KHMETIS for the function f λ .Note that our approach sometimes allows a better solution for both f p and f λ .V. CONCLUSION In this paper, we present a multilevel approach to the problem of red-black hypergraph (circuit) partitioning on not fully connected topologies.Our approach consists of exploiting the vertices' criticality to group the critical paths in the same part during the coarsening phase.Finally, we propose a mathematical model considering the two objectives: f p and f λ for the initial partitioning.For the refinement, we use the DKFM algorithm.Our results show that our approach is better at minimizing f p than a min-cut partitioning tool, even if it is oriented towards the criticality of hyperarcs.It may be interesting to test our approach on other more extensive benchmarks, as well as to test other coarsening algorithms to improve the results of initial partitioning based on our IP.
(i ∈ O l ), where O l1 and O ln ′ are the first and the last elements of O l

Table V
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TABLE IV RESULTS
FOR PATH-COST fp IN NANO-SECONDE (NS)

TABLE V RESULTS
FOR CONNECTIVITY f λ