Logo ICITKM

Annals of Computer Science and Information Systems, Volume 14

Proceedings of the 2017 International Conference on Information Technology and Knowledge Management

Logo PTI

Application of ASIP in Embedded Design with Optimized Clock Management

, ,

DOI: http://dx.doi.org/10.15439/2017KM41

Citation: Proceedings of the 2017 International Conference on Information Technology and Knowledge Management, Ajay Jaiswal, Vijender Kumar Solanki, Zhongyu (Joan) Lu, Nikhil Rajput (eds). ACSIS, Vol. 14, pages 159–163 ()

Full text

Abstract. As the demand for high performance computing increases, new approaches have to be found to automate the design of embedded processors. Simultaneously, new tools have to be developed to short the execution time consumption, and simpler design resulting in time to market. These are to be applied for the system architecture to achieve rapid exploration in on power consumption, chip area, and performance constraints. This enables interest in Application Specific Instruction Processors (ASIPs) design and application considerably. It has higher flexibility as compared to dedicated hardware. The current case study focuses on an ASIP design methodology considering the classical parameters computational performance and area as well as energy consumption simultaneously. In this paper, the clock gating is analyzed and designed. Further it is optimized using Fast genetic algorithm (FastGA). The optimization result is shown for ICORE (ISS-core) ASIP for DVB-T acquisition and tracking algorithms. Observation shows a potential of about one order of magnitude in savings of energy for optimization.

References

  1. R. White, F. Muller, C. Healy, D. Whalley, and M. Harmon,“Timing Analysis for Data Caches and Set-Associative Caches,” in Proc. 3rd IEEE Real-Time Technology andApplications Symposium (RTAS’97), Jun 1997, pp. 192–202.
  2. J. Engblom and A. Ermedahl, “Pipeline Timing Analysis Using a Trace-Driven Simulator,” in Proc. 6th International Conference on Real-Time Computing Systems and Applications(RTCSA’99). IEEE Computer Society Press, Dec1999.
  3. M. Arnold and H. Corporaal, “Designing domain-specific processors,” In Proc. Codesign Symposium 2001.
  4. A. Alomaryet al., “PEAS-I: A hardware/software co-design system for ASIPs,” In Proc. EURO-DAC 1993.
  5. J. Van Praetet al., "Instruction set definition and instruction selection for ASIPs," In Proc. HLS Symposium 1994.
  6. N. Clark, H. Zhong and S. Mahlke, “Processor Acceleration Through Automated Instruction Set Customization”. In Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture (MICRO 36), 2003.
  7. R. Klemm, J. P. Sabugo, H. Ahlendorf and G. Fettweis, “Using LISATek for the Design of an ASIP core includingFloating Point Operations”, Technical report, 2008.
  8. R. R. Hoare et al., “Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions”. EURASIP Journal on Applied Signal Processing, vol. 2006 ID 46472, 2010.
  9. F. Tlili and A. Ghorbel, “ASIP Solution for Implementation of H.264 Multi Resolution Motion Estimation”. In theInternational Journal of Communications, Network and System Sciences, Vol.3 No.5, May 2010.
  10. G. Kappen, L. Kurz, O. Priebe and T. G. Noll, “Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers”. Journal of Signal Processing Systems, vol. 58 (1), pp. 41-51, 2010.
  11. ChristophSteiger, Herbert Walder, Marco Platzner, and Lothar Thiele. 2003. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proc. of Real-Time Syst. Symp. IEEE,224–225.
  12. Pan Yu and TulikaMitra. 2004. Scalable custom instructions identification for instruction-set extensible processors. In Proc. of Int. Conf. on Compilers, Architecture and Synthesis for Embed. Syst. ACM, 69–78.
  13. Pan Yu and TulikaMitra. 2005. Satisfying real-time constraints with custom instructions. In Proc. Int. Conf.on Hardware/Software Codesign and System Synthesis. IEEE, 166–171.
  14. C. Mead, L. Conway: Introduction to VLSI Systems, Addison-Wesley, 1980.
  15. N. Weste, K. Eshraghain: Principles of CMOS VLSI Design, Addison-Wesley, 1985.
  16. L. A. Glasser D. W. Dobberpuhl: The Design and Analysis of VLSI Circuits, Addison- Wesley, 1985.
  17. Sato, J.; Imai, M.; Hakata, T.; Alomary, A.Y.; Hikichi, N. : “An integrated design environment for application specific integrated processor.”, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers andProcessors 1991, ICCD ’91, 14-16 Oct. 1991, Pages: 414-417.
  18. R. R. Hoare et al., “Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions”. EURASIP Journal on Applied Signal Processing, vol. 2006 ID 46472, 2010.
  19. Sato, J.; Imai, M.; Hakata, T.; Alomary, A.Y.; Hikichi, N. : “An integrated design environment for application specific integrated processor.”, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers andProcessors 1991, ICCD ’91, 14-16 Oct. 1991, Pages: 414-417.
  20. Liem, C.; May, T.; Paulin, P. : “Instruction-set matching and selection for DSP and ASIP code generation.”, Proceedings ofthe European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC EuropeanTest Conference. EUROASIC, 28 Feb.-3 March 1994, Pages: 31-37.
  21. Praet J.V.; Goossens, G.; Lanneer, D.; De Man, H.: “Instruction set definition and instruction selection for ASIPs.”, Proceedingsof the Seventh International Symposium on High-Level Synthesis 1994, 18-20 May 1995, Pages: 11-16.
  22. L. Benini, G.D. Micheli, E. Macii, M. Poncino, and R. Scarsi, “Symbolic synthesis ofclock-gating logic for power optimization of synchronous controllers,” ACM Trans. Des.Autom. Electron. Syst., vol.4, no.4, pp.351–375, 1999.
  23. Jorg Henkel,Lars Bauer, Michael Hubner and Artjom Grudnitsky,2011. I-core: A run-time adaptive processor for embedded multi-core systems. In Proc. Int. Conf.on Engineering of Reconfig. Syst. And Algorithms.