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Annals of Computer Science and Information Systems, Volume 24

Proceedings of the 2020 International Conference on Research in Management & Technovation

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Implementing Cyclic Redundancy Check as Error Correction Technique in HDLC

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DOI: http://dx.doi.org/10.15439/2020KM13

Citation: Proceedings of the 2020 International Conference on Research in Management & Technovation, Shivani Agarwal, Darrell Norman Burrell, Vijender Kumar Solanki (eds). ACSIS, Vol. 24, pages 131136 ()

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Abstract. Any successful communication is governed by some set of rules to manage the flow control of the transmitted data. One such protocol is High-level Data Link Control (HDLC) which is a bit-oriented protocol used for communication over the point to point or multipoint links. Residing in the data link layer (layer 2) of Open System Interconnection (OSI), this protocol transmits data in frames. HDLC can be used for detecting the errors in the data which are induced during the transmission from sender to receiver. This paper focuses on not only detecting the error but also correcting it by using Cyclic Redundancy Check (CRC). Cyclic codes are a special type of linear Block Codes in which one codeword can be cyclically shifted to obtain another codeword. The CRC generator is modulo-2 added with the data in the information frame of HDLC and the remainder is obtained. When this data is sent over any transmission channel, there are high chances of data being erroneous due to interference of unrequired signals in the channel. When data reaches the receiver end, a similar modulo-2 addition is carried to obtain another remainder. This remainder is compared with the remainder transmitted by the sender. The two compared remainders detect the location of the error bit which is corrected by flipping that specific bit. This reduces the need for Automatic Repeat Request (ARQ) mechanisms to obtain the correct information as the data can be self-corrected at the receiver end.


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