Data Structures for Markov Chain Transition Matrices on Intel Xeon Phi
Beata Bylina, Joanna Potiopa
Citation: Proceedings of the 2016 Federated Conference on Computer Science and Information Systems, M. Ganzha, L. Maciaszek, M. Paprzycki (eds). ACSIS, Vol. 8, pages 665–668 (2016)
Abstract. We employ Intel Xeon Phi as a high-performance coprocessor to solve Markov chains. Matrices arising from Markov models are very sparse with short rows. In this paper the authors research two storage formats of Markov chain transition matrices on Intel Xeon Phi. In this work are studies CSR and HYB (modification ELL) format for such matrices. Using these formats, sparse matrix-vector multiplication (SpMV) operation is implemented and then is employed to the explicit fourth- order Runge-Kutta method. Numerical experiments results for transition matrices of Markov chains from wireless networks and call-center models show that HYB format in offload version is more effective than CSR format. The obtained performance for HYB format is even 1.45 times better in comparison to multi- threaded CPU (dual Intel Xeon E5-2670) with the use of the CSR format (SpMV from the MKL library on CPU).
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